1. Field of the Invention
The present invention is related to a semiconductor device and a method of fabrication thereof.
2. Description of the Related Art
There is a growing need for a smaller semiconductor device package with multiple terminal pins due to increases of an integration rate and an operation frequency in the recent semiconductor device. However, a package size of a conventional peripheral terminal type utilizing a leadframe has to be made larger if a number of the terminals should be increased further. One of countermeasures is to decrease a terminal pitch in the package. However, it is difficult to make the terminal pitch narrower than 0.4 mm.
To accommodate such increasing number of the terminals, an area array type package with its terminals disposing over a surface plane is introduced. The area array type package requires to have a wiring substrate for providing wiring from chip terminals to external terminal electrodes. The chip may be mounted either at the upper surface or the lower surface of the wiring substrate when the external terminal electrodes are disposed at the lower surface of the wiring substrate. When the chip is mounted on the upper surface of the wiring substrate, interlayer connections between the upper surface and the lower surface of the wiring substrate have to be provided. When the chip is mounted on the lower surface of the wiring substrate, the interlayer connections will not be required. However, a hollow space has to be provided to absorb total thickness of the chip and its sealing material when the chip is mounted on the lower surface of the wiring substrate.
The hollow space is called a cavity, and a structure with the cavity at the lower surface of the wiring substrate is called a cavity down structure. Typically, the structure can be made by hollowing out a substrate, or by making a hole through the substrate and adhering a base plate thereto. Wiring for a multiple layer structure is required when heights of chip bonding portions and external electrodes are changed because the wiring is also disposed on the same surface in this structure. According to the methods described above, a wiring structure, which satisfies required conditions for a three dimensional spatial relationships among the chip mount portion, the chip bonding portion and the external electrode portion.
One of the area array type semiconductor package is Ball Grid Array (BGA) in which solder balls are used as connection terminals. Cost of the BGA is higher than that of a semiconductor device fabricated with a conventional leadframe, and reduction of the cost is anticipated. The higher cost is due to a fact that a structure and fabricating process of the semiconductor chip package substrate are more complex than that of a substrate with the leadframe. Accordingly, it is anticipated the development of simpler structure and fabricating process of the semiconductor chip package substrate.
The wiring substrate used for the area array type semiconductor package is typically called an interposer. The interposer may be roughly classified into a film type and a rigid type. A number of the wiring layers can be either one, or two, or three and more layers. Generally, the fabricating cost is lower for a fewer number of the wiring layers.
The lowest cost is expected with the single layer wiring structure. If the wiring is disposed at least in both surfaces of the interposer, the semiconductor chip mount portion and the external terminals may be divided at the upper and the lower surfaces. However, the semiconductor chip mount portion and the external terminals are disposed on the same surface of the interposer with the single layer wiring structure. In such a single layer wiring structure, it is required to have the cavity portion on the wiring surface with a depth at least comparable to a thickness of the chip so as to store the chip therein. A method of fabricating such a cavity portion has become an important subject.
In the interposer so called TAB (Tape Automated Bonding) or TCP (Tape Carrier Package) and their packaging technology, the center portion of the interposer is bored through to store the semiconductor chip. With the rigid plate, the center portion of the interposer is similarly bored through to hollow the semiconductor chip store portion out and adhere a metal plate as the base plate thereto, or the cavity portion is fabricated at the center portion of the interposer. The wiring is disposed only in a flat plane portion, not inside the cavity portion.
In conventional semiconductor devices employing lead frames, transfer molding has been in wide use for their fabrication. However, in the fabrication of semiconductor devices in recent years where semiconductor chips are mounted on substrates, the transfer molding, which requires expensive and long-time-to-delivery molds, has become adaptable with difficulty though still used in some cases, because it is difficult for the substrates used and package structure to be standardized.
Accordingly, liquid resin encapsulation (sealing) is highlighted which requires no mold and is suited especially when small quantity and many kinds of products are manufactured in a short time to delivery. Dispensing, printing and vacuum pressure differential printing are known as chief methods for such encapsulation making use of a liquid resin encapsulant (sealant).
FIG. 24C perspectively illustrates an encapsulation target where a semiconductor chip 1 is mounted on a substrate 7 and this chip 1 and a conductor wiring 2 are connected through wires 3 by wire bonding. In conventional dispensing, as shown in FIG. 24A, a solder resist 25 is provided on the surface of the conductor wiring 2 of this chip-mounting substrate. On that surface an encapsulation dam 26 is provided as shown in FIG. 24B, and a liquid resin encapsulant 4 is poured therein to encapsulate the chip 1 as shown in FIG. 24D. In this method, however, especially in the case of fine-pitch wire bonding, the resin encapsulant 4 may come around with difficulty beneath the wires 3 at the time of encapsulation to tend to cause encapsulation defects 20 such as air bubbles and faulty filling, also resulting in a low productivity.
Printing is known as a liquid resin encapsulation method that can achieve a productivity comparable to that of transfer molding. The printing is a method in which as shown in FIG. 25A an encapsulant 4 is printed via a printing mask 28 and thereafter as shown in FIG. 25B the printing mask 28 is removed, whereby a chip 1 is encapsulated. This method promises a high productivity, but, in the case of fine-pitch wire bonding, tends to cause encapsulation defects 20 such as faulty filling and air bubbles beneath bonded wires 3 or at the part with complicated or delicate internal structure.
As a method for solving this problem to achieve improvement greatly, there is vacuum pressure differential printing, which has been invented so that printed portions with complicated internal structure can be filled with a printing resin without leaving any air bubbles.
In this method, the whole printing portions, i.e., part or the whole of a printing device, a printing mask 28, a liquid resin encapsulant 4, and a printing-target wiring substrate 1 with a semiconductor chip mounted thereon, and so forth, are placed in a vacuum container, where first-time printing is carried out firstly in the state the vacuum container is kept at a high vacuum (FIG. 26A). When left in this state, any delicate areas of printed portions can be filled with the resin with difficulty, so that an empty space 21 may remain.
Accordingly, the vacuum container is then brought to medium-vacuum condition, whereupon the high-vacuum empty space 21 not filled with the resin at the first-time printing is crushed up to the medium-vacuum condition to become almost free of the empty space 21 and simultaneously a depression 22a appears at the resin surface to an extent corresponding to the resin with which the open space has been filled (FIG. 26B).
In that state, second-time printing is carried out as it is kept in medium vacuum, to fill up the depression 22a of the resin surface (FIG. 26C). Thereafter, the vacuum is returned to atmospheric pressure, the printing mask 28 is removed, and the printed article is taken out, thus the resin encapsulation is completed.
During the first-time printing (FIG. 26A) carried out in high vacuum, the empty space 21 comes into being where the resin has not been packed into any delicate areas lying beneath bonding wires. Here, if the resin layer lying above the empty space 21, i.e., the resin layer formed on the bonding wires 3 has a thickness smaller than the depth of the high-vacuum empty space 2121 lying beneath the wires 3, the resin layer may break when the resin is sucked in the high-vacuum empty space 21 during the printing carried out in medium-vacuum condition, so that the empty space or air bubbles 22 kept in medium vacuum may remain in the resin (FIG. 26B). This phenomenon is called a pressure differential short circuit.
Even if in this state the resin for the portion of the depression, corresponding to the resin sucked therein, is supplied by the second-time printing, air bubbles 20 may remain as shown in FIG. 26C, at the time the vacuum is returned to atmospheric pressure. In order to prevent the pressure differential short circuit from being caused when returned to medium vacuum, the resin layer on the bonding wires 3 may beforehand be formed in a sufficiently large thickness. However, a resin layer merely made to have a large thickness makes the package have too large a thickness, and also may bring about a difficulty in the mounting on a mother board because of a protrusion of encapsulation resin when the encapsulation surface and the external terminal surface are identical.
Thus, the vacuum pressure differential printing, though promising a high productivity and usually less causing encapsulation defects, has had a problem that the encapsulation defects (such as air bubbles) 20 tends to come into being once the pressure differential short circuit has occurred.
An object of the present invention is to obtain a semiconductor device that is compact and inexpensive, has a high reliability and makes it easy to standardize designing and fabrication steps, without causing any encapsulation defects.
The present invention provides a semiconductor device fabrication process comprising an encapsulation step of carrying out encapsulation by vacuum pressure differential printing by the use of a liquid resin encapsulant containing a solvent in an amount of from 5% by weight to 50% by weight, and preferably from 25% by weight to 50% by weight.
The fabrication process of the present invention may further be provided, before the encapsulation step, with;
a mounting step of mounting a semiconductor chip on a substrate having on its surface a surface wiring and a first hollow place (cavity portion), being provided with a second hollow place in a bottom area of the first hollow place and having an internal connecting terminal on the inner wall of the first hollow place; the semiconductor chip being mounted in a bottom area of the second hollow place; and
a wire-connecting step of interconnecting the internal connecting terminal and the semiconductor chip through a wire. Here, the encapsulation step is the step of encapsulating at least the internal connecting terminal, the semiconductor chip and the wire. Also, the wire may preferably be held in the interior of the first hollow place and second hollow place (i.e., the wire is positioned lower than the surface of the substrate on which the surface wiring is provided).
The encapsulation step in the fabrication process of the present invention may preferably be the step of printing a liquid resin encapsulant by vacuum pressure differential printing in such a way that the encapsulant covers at least the internal connecting terminal provided on the substrate, the semiconductor chip, and the wire interconnecting the internal connecting terminal and the semiconductor chip, and that the thickness of the encapsulant lying above the wire at the highest position (hereinafter xe2x80x9cthe apexxe2x80x9d) of the wire (i.e., at the position close to the encapsulant surface or the surface laid bare to the atmosphere), i.e., the thickness extending from the apex of the wire to the encapsulant surface (the surface laid bare to the atmosphere) comes to be at least 0.8 time the thickness of the encapsulant lying beneath the wire at the same position (i.e., the thickness extending from the apex of the wire to the bottom of the encapsulated portion), and curing or drying the encapsulant.
The present invention also provides a semiconductor device comprising;
a substrate having on its surface a surface wiring and a first hollow place, being provided with a second hollow place in a bottom area of the first hollow place and having an internal connecting terminal on the inner wall of the first hollow place;
a semiconductor chip bonded to a bottom area of the second hollow place;
a wire interconnecting the internal connecting terminal and the semiconductor chip; and
an encapsulation member which encapsulates at least the internal connecting terminal, the semiconductor chip and the wire.
Here, the wire may preferably be held in the interior of the first hollow place and second hollow place (i.e., the wire are positioned lower than the surface of the substrate on which the surface wiring is provided). Also, the sidewall of the first hollow place may preferably has a slant, and the wire interconnecting the surface wiring and the internal connecting terminal are provided at the slant.
The present invention still also provides a liquid encapsulant comprising a solvent contained in an amount of from 5% by weight to 50% by weight, and preferably from 25% by weight to 50% by weight, and its use in vacuum pressure differential printing. The present invention is suitable for a semiconductor chip package substrate with a cavity portion, or a semiconductor device fabricated by mounting at least one semiconductor chip in the cavity portion and sealing with plastic sealant, wherein said semiconductor chip package substrate comprises wiring disposed along a surface of the substrate and wall surfaces of the substrate in the cavity portion, the wiring comprises an external connection terminal portion for connecting to external connection terminals which are provided on the surface of the substrate at a side of the cavity portion""s opening, an internal connection terminal portion for connecting to the mounted semiconductor chip, and a wiring portion disposed in between the external connection terminal portion and the internal connection terminal portion, the wiring portion is buried in a surface of the substrate and one of said wall surfaces of the substrate in the cavity portion and the internal connection terminal portion is disposed inside of the cavity portion.
For example, the wall surface of the substrate in the cavity portion may be extended toward the bottom surface of the cavity portion with a slant angle which is set within a predetermined angle range. Concretely, the slant angle may be within a range of 5-40xc2x0, and preferably within a range of 10-40xc2x0. The slant structure may be fabricated so as that a ratio L/G is within a range of 1.5 less than L/G less than 10, where G is a height of the slant structure of the wall surface of the substrate in the cavity portion, and L is its horizontal dimension. More preferable range of the ratio L/G is 2 less than L/G less than 10, and the most preferable range is 3 less than L/G less than 10.
The cavity portion is, for example, formed by a press forming process utilizing a press pattern with a projected portion. The cavity portion may also be formed into a multiple step structure.
Alternatively, the cavity portion may be provided with a semiconductor chip mount portion for mounting semiconductor chip, which is formed by hollowing the cavity portion out further. A depth of the semiconductor chip mount portion which has been hollowed out is preferably larger than a thickness of a semiconductor chip to be mounted therein.
Furthermore, a height of a ramp between the external connection terminal portion disposed on the substrate surface and the internal connection terminal portion disposed inside of the cavity portion may be preferably not less than 0.05 mm in the semiconductor chip package substrate and the semiconductor device according to the present invention.
The terminals of the semiconductor chip mounted inside of the cavity portion and the internal connection terminal portions are wire-bonded, or, directly connected by a face-down bonding.
Furthermore, the wiring in the semiconductor chip package substrate and the semiconductor device according to the present invention may be preferably disposed in an area of the wall surface which does not include any of corner sections of the cavity portion.
Furthermore, the cavity portion may be formed substantially at the center of the major surface plane of the substrate, and the semiconductor chip may be mounted inside of the cavity portion so as the semiconductor chip to be positioned substantially at the center of a dimension of the thickness of the semiconductor chip package substrate. Alternatively, the semiconductor chip may be offset-mounted in the cavity portion with an offset amount of not bigger than 30% of the substrate thickness from the center position of the substrate""s thickness along a direction of the thickness. The cavity portion may have a size large enough to mount a plurality of device elements on its bottom surface area, and may be provided with a plurality of wiring sets to the plurality of device elements, and a plurality of semiconductor chips and passive device elements may be mounted in the cavity portion.
Furthermore, the wiring in the semiconductor chip package substrate and the semiconductor device according to the present invention is preferably formed by utilizing a squeeze shapeable wiring construction body consisting of only metals, the squeeze shapeable wiring construction body having a multiple layer structure including at least the first metal layer for constructing the wiring and the second metal layer which functions as a carrier layer.
Furthermore, a depth of the cavity portion may be less than a thickness of the semiconductor chip to be mounted, and the cavity portion may be hollowed out at the bottom surface of the cavity portion from the center portion along a direction of a thickness of the semiconductor chip package substrate up to a depth within a range of 0.5-2.5 times a thickness of the semiconductor chip to be mounted. Alternatively, a depth of the cavity portion may be less than a thickness of the semiconductor chip to be mounted, and the cavity portion may be hollowed out at the bottom surface of the cavity portion, and the semiconductor chip package substrate may be further comprising a plastic layer formed by hardening prepregs so as to have an exposed hollowed-out bottom surface at least consisting of nonwoven fabrics.
In this case, a metal plate with a thickness of not less than 0.035 mm may be adhered to a reverse side of the plastic layer wherein the cavity portion was formed, a depth of the cavity portion may be made to be less than a thickness of the semiconductor chip to be mounted, and the bottom of the cavity portion may be hollowed out to expose the metal plate. Alternatively, a metal plate with a thickness of not less than 0.20 mm may be adhered to the reverse side of the plastic layer wherein the cavity portion was formed, a depth of the cavity portion may be made to be less than a thickness of the semiconductor chip to be mounted, and the bottom of the cavity portion may be hollowed out into the metal plate as much as the hollowed out depth in the metal plate is not less than 0.05 mm.
Furthermore, the hollow-out process of the plastic layer may be stopped before reaching the metal plate.
The above object of the present invention may be accomplished by a fabricating method of a semiconductor chip package substrate, comprising the steps of: pressing to adhere a squeeze shapeable wiring construction body to a plastic substrate, the wiring construction body consisting of all metals and having a multiple layer structure comprising at least the first metal layer and the second metal layer which functions as a carrier layer; coincidentally shaping the plastic substrate so as to form a cavity portion therein with its wall surfaces having inclination angles within a predetermined range; and removing the metal layers except the first layer; wherein the wiring, which is buried in the substrate surface and wall surface of the substrate in the cavity portion, is formed and disposed along the substrate surface and the wall surface of the substrate in the cavity portion; and the wiring comprising an external connection terminal portion for connecting to external connection terminals disposed on a surface of the substrate on a side of the cavity opening, an inner connection terminal portion for connecting to a semiconductor chip to be mounted, and a wiring portion in between the external connection terminal portion and the inner connection terminal portion.
A percentage elongation after fracture of the squeeze shapeable wiring construction body is preferred to be not less than 2%. A thickness of the carrier layer composing the squeeze shapeable wiring construction body is preferred to be within a range of 0.010-0.050 mm. A slant angle range of the wall surface of the substrate in the cavity portion is preferred to be from 5xc2x0 to 40xc2x0, and a depth of the cavity portion is preferred to be at least not less than 30% of a thickness of a semiconductor chip to be mounted. The hollow-out process may be performed on the bottom surface of the cavity portion after the cavity portion is formed, and after the hollow-out process, other metal layers may be removed. Performing the hollow-out process while having the other metal layers enable to increase a process accuracy at hollowed out edges.
The above object of the present invention may be accomplished by a fabricating method of a semiconductor chip package substrate having at least one cavity portion for mounting at least one semiconductor chip and wiring, comprising the steps of: a step for making a depth of the cavity portion less than a thickness of a semiconductor chip to be mounted, and a step for hollowing out the cavity portion at the bottom surface, wherein the wiring to the semiconductor chip mounted is cut during the hollow-out process, and the cut edge portion of the wiring reaches a fringe portion of a cavity portion formed by the hollow-out process. A process accuracy at edges of the cavity portion increase.
According to the present invention, a fine pitch wiring corresponding to a connection pitch of the semiconductor chip may be disposed while forming the cavity portion which is capable of mounting the semiconductor chip, and is suitable for an area array type semiconductor package. The semiconductor package utilizing this technology is suitable for CSP (Chip Scale Package), FBGA (Fine Pitch Ball Grid Array), BGA (Ball Grid Array), LGA (Land Grid Array) or the like.